I for got to add that I am sure that there is a standard EPROM that is compatable with the Chry P/Ns. If all else fails, I can trace the EEPROM datalines and construct the pin out, and use trial-and-error to acheive a coherent ROM dump.
I have a 1985 Laser XE cluster on my benchtop right now with the ODO chip signals on the logic analyzer. You have to be careful as there are two negative power supplies to the chip. There is a -5 which probably would not kill my test equipment, but the apparent programming voltage(always present) is -30V!
I started by probing each pin with a volt meter to try and determine the power supplies. There were several pins that are always low, so I'm not sure which of those are the actual ground power pin. One pin seemed to be steady +5 V, so I'm assuming that's the main Vdd. The negative programming voltage is curious, most EEPROMs I've seen use +27V or so for programming. -5 V is not unusual for older chips. Perhaps this is an NMOS device and not full CMOS?
I could only identify five signals that actually toggled during the apparent read cycles(On power up) or write cycles (On 12V ign powerdown with 12V batt still powered). This suggests that the device is in some manner serial instead of parallel which will make decoding a bear.
With the apparent writes, the signaling made some sense with one of the signals appearing to be a clock or strobe of some sort. The period was 80uS which looks right, but I haven't figured out which signal(s) are data, chip select, rd/wr yet. Also, there seem to be a very large number of repeated bursts for the shutdown sequence compared to the startup read sequence which looks like one single burst after some sort of setup sequence.
Reads look totally different, where the writes look slow and synchronous, the reads look completely asynchronous, and the signal timing looks impossible. There are several short (10-20ns) pulses and delays that can't possibly be actual chip timings as there is no way 1984 automotive technology was running at 50-100MHz. What looks like synchronous 10-20ns setup/hold timings must be the actual propagation delays of these old devices. I clearly have more work to do here...